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? semiconductor components industries, llc, 2006 november, 2006 ? rev. p2 1 publication order number: ncp1351/d ncp1351 product preview variable off time pwm controller the ncp1351 is a current?mode controller targeting low power off?line flyback switched mode power supplies (smps) where cost is of utmost importance. based on a fixed peak current technique (quasi?fixed t on ), the controller decreases its switching frequency as the load becomes lighter. as a result, a power supply using the ncp1351 naturally offers excellent no?load power consumption, while optimizing the efficiency in other loading conditions. when the frequency decreases, the peak current is gradually reduced down to approximately 30% of the maximum peak current to prevent transformer mechanical resonance. the risk of acoustic noise is thus greatly diminished while keeping good standby power performance. an externally adjustable timer permanently monitors the feedback activity and protects the supply in presence of a short?circuit or an overload. once the timer elapses, ncp1351 stops switching and stays latched for version a, and tries to restart for version b. the internal structure features an optimized arrangement which allows one of the lowest available startup current, a fundamental parameter when designing low standby power supplies. the negative current sensing technique minimizes the impact of the switching noise on the controller operation and of fers the user to select the maximum peak voltage across his current sense resistor. its power dissipation can thus be application optimized. finally, the bulk input ripple ensures a natural frequency smearing which smooths the emi signature. features ? quasi?fixed t on , variable t off current mode control ? extremely low current consumption at startup ? peak current compression reduces transformer noise ? primary or secondary side regulation ? dedicated latch input for otp, ovp ? programmable current sense resistor peak voltage ? natural frequency dithering for improved emi signature ? easy external over power protection (opp) ? undervoltage lockout ? very low standby power via off?time expansion ? internal temperature shutdown ? soic?8 package typical applications ? auxiliary power supply ? printer, game stations, low?cost adapters ? off?line battery charger this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. soic?8 d suffix case 751 1 8 marking diagram pin connections x = a, b, c, or d options a = assembly location y = year ww = work week = pb?free device 1 fb 8 timer 2 ct 3 cs 4 gnd 7 latch 6 v cc 5 drv (top view) 1351x ayww device package shipping ? ordering information ncp1351adr2g soic?8 (pb?free) 2500 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 1 8 http://onsemi.com NCP1351BDR2G soic?8 (pb?free) 2500 / tape & ree l
ncp1351 http://onsemi.com 2 figure 1. typical application circuit 1 8 2 3 4 7 6 5 85?265vac + + *opp ncp1351 + latch gnd v out *optional pin function description pin n pin name function pin description 1 fb feedback input injecting current in this pin reduces frequency 2 ct oscillator frequency a capacitor sets the maximum switching frequency at no feedback current 3 cs current sense input senses the primary current 4 gnd ? ? 5 drv driver output driving pulses to the power mosfet 6 v cc supply input supplies the controller up to 28 v 7 latch latchoff input a positive voltage above v latch fully latches off the controller 8 timer fault timer capacitor sets the time duration before fault validation
ncp1351 http://onsemi.com 3 internal circuit architecture figure 2. a version (latched short?circuit protection) fb timer ct cs g nd latch v cc drv ? + ? + ? + ? + ? + uvlo reset fault = low s r 1 s pulse v cc mngt s r v dd v dd + + + + + v dd clamp uvlo reset v zener vcc stop 1 = ok 0 = not ok v latch i timer 20 s filter 20 s filter i p flag ic t q q q q 4v reset 45k v offset v dd ics?dif* ics?dif* ics?min* vth *(ics?diff = ics?max ?ics?min) v timer v fault v dd
ncp1351 http://onsemi.com 4 fb timer ct cs g nd latch v cc drv ? + ? + ? + ? + ? + uvlo reset fault = low s r 1 s pulse v cc mngt s r v dd v dd + + + + + v dd clamp uvlo reset v zener vcc stop 1 = ok 0 = not ok v latch i timer 20 s filter i p flag ic t q q q q 4v reset 45k v offset v dd ics?dif* ics?dif* ics?min* vth *(ics?diff = ics?max ?ics?min) figure 3. b version (auto?recovery short?circuit protection) s r q q vi timer v fault v dd
ncp1351 http://onsemi.com 5 maximum ratings symbol rating value unit v supply maximum supply on v cc pin 6 ?0.3 to 28 v i supply maximum current in v cc pin 6 20 ma v drv maximum voltage on drv pin 5 ?0.3 to 20 v i drv maximum current in drv pin 5 400 ma v max supply voltage on all pins, except pin 6 (v cc ), pin 5 (drv) ?0.3 to 10 v i max maximum current in all pins except pin 6 (v cc ) and pin 5 (drv) 10 ma i fbmax maximum injected current in pin 1 (fb) 0.5 ma r gmin minimum resistive load on drv pin 33 k r ja thermal resistance junction?to?air 200 c/w t jmax maximum junction temperature 150 c storage temperature range ?60 to +150 c esd capability, human body model v per mil?std?883, method 3015 2 kv esd capability, machine model 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device contains latchup protection and exceeds 100 ma per jedec standard jesd78.
ncp1351 http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?25 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section and v cc management vcc on v cc increasing level at which driving pulses are authorized 6 15 18 22 v vcc stop v cc decreasing level at which driving pulses are stopped 6 8.3 8.9 9.5 v vcc hyst hysteresis vcc on ? vcc stop 6 6 ? ? v v zener clamped v cc when latched off / burst mode activation 6 ? 6 ? v icc1 startup current 6 ? ? 10 a icc2 internal ic consumption with i fb = 50 a, f sw = 65 khz and c l = 0 6 ? 1.0 1.8 ma icc3 internal ic consumption with i fb = 50 a, f sw = 65 khz and c l = 1 nf 6 ? 1.6 2.5 ma icc latch current flowing into v cc pin that keeps the controller latched 6 20 ? ? a current sense i csmin minimum source current (i fb = 90 a) t j = 0 c to +125 c 3 61 70 75 a i csmin minimum source current (i fb = 90 a) t j = ?25 c to +125 c 3 58 70 75 a i csmax maximum source current (i fb = 50 a) t j = 0 c to +125 c 3 251 270 289 a i csmax maximum source current (i fb = 50 a) t j = ?25 c to +125 c 3 242 270 289 a v th current sense comparator threshold voltage 3 10 20 35 mv t delay propagation time delay (cs falling edge to gate output) 3 ? 160 300 ns timing capacitor v offset minimum voltage on c t capacitor, i fb = 30 a 2 475 510 565 mv vct max voltage on c t capacitor at i fb = 150 a 2 5 ? ? v i ct source current (ct pin grounded) 2 10 11 12 a vct min minimum voltage on c t , discharge switch activated 2 ? ? 20 mv t disch c t capacitor discharge time (activated at drv turn?on) 2 1 s v fault c t capacitor level at which fault timer starts a, b versions 2 0.4 0.5 0.6 v feedback section v fb fb pin voltage for an injected current of 200 a 1 ? 0.7 ? v i fault fb current under which a fault is detected a, b versions 1 ? 40 ? a i fbcomp fb current at which cs compression starts 1 ? 60 ? a i fbred fb current at which cs compression is finished 1 ? 80 ? a drive output t r output voltage rise?time @ cl = 1 nf, 10 ? 90% of output signal 5 ? 90 ? ns t f output voltage fall?time @ cl = 1 nf, 10 ? 90% of output signal 5 ? 100 ? ns r oh source resistance 5 ? 80 ? r ol sink resistance 5 ? 30 ? v drvlow drv pin level at v cc close to vcc stop with a 33 k resistor to gnd 5 8.0 ? ? v v drvhigh drv pin level at v cc = 28 v 5 16 17 20 v protection i timer timing capacitor charging current 8 10 11.5 13 a v timer fault voltage on pin 8 8 4.5 5 5.5 v t timer fault timer duration, c timer = 100 nf ? ? 42 ? ms v latch latching voltage 7 4.5 5 5.5 v
ncp1351 http://onsemi.com 7 the ncp1351 implements a fixed peak current mode technique whose regulation scheme implements a variable switching frequency. as shown on the typical application diagram, the controller is designed to operate with a minimum number of external components. it incorporates the following features: ? frequency foldback: since the switching period increases when power demand decreases, the switching frequency naturally diminishes in light load conditions. this helps to minimize switching losses and offers good standby power performance. ? very low startup current: the patented internal supply block is specially designed to offer a very low current consumption during startup. it allows the use of a very high value external startup resistor, greatly reducing dissipation, improving efficiency and minimizing standby power consumption. ? natural frequency dithering: the quasi?fixed t on mode of operation improves the emi signature since the switching frequency varies with the natural bulk ripple voltage. ? peak current compression: as the load becomes lighter, the frequency decreases and can enter the audible range. to avoid exciting transformer mechanical resonances, hence generating acoustic noise, the ncp1351 includes a patented technique, which reduces the peak current as power goes down. as such, inexpensive transformer can be used without having noise problems. ? negative primary current sensing: by sensing the total current, this technique does not modify the mosfet driving voltage (v gs ) while switching. furthermore, the programming resistor, together with the pin capacitance, forms a residual noise filter which blanks spurious spikes. ? programmable primary current sense : it offers a second peak current adjustment variable, which improves the design flexibility. ? extended v cc range: by accepting v cc levels up to 28 v, the device offers added flexibility in presence of loosely coupled transformers. the gate drive is safely clamped below 20 v to avoid stressing the driven mosfet. ? easy opp: connecting a resistor from the cs pin to the auxiliary winding allows easy bulk voltage compensation. ? secondary or primary regulation: the feedback loop arrangement allows simple secondary or primary side regulation without significant additional external components. ? latch input: if voltage on pin 7 is externally brought above 5 v, the controller permanently latches off and stays latched until the user cycles v cc down, below 4 v typically. ? fault timer: in presence of badly coupled transformer, it can be quite difficult to detect an overload or a short?circuit on the primary side. when the feedback current disappears, a current source charges a capacitor connected to pin 8. when the voltage on this pin reaches a certain level, all pulses are shut off and the v cc voltage is pulled down below the vcc (min) level. this protection is latched on the a version (the controller must be shut down and restart to resume normal operation), and auto?recovery on version b (if the fault goes away, the controller automatically resumes operation).
ncp1351 http://onsemi.com 8 application information the negative sensing technique standard current?mode controllers use the positive sensing technique as portrayed by figure 4. in this technique, the controller detects a positive voltage drop across the sense resistor, representative of the flowing current. unfortunately, this solution suffers from the following drawbacks: 1. difficulties to precisely adjust the peak current. if 1 v is the maximum sense level, you must combine low valued resistors to reach the exact limit you need. 2. the voltage developed across the sense resistor subtracts from the gate voltage. if your vcc (min) is 7 v, then the actual gate voltage at the end of the on time, assuming a full load condition, is 7 v ? 1 v = 6 v. 3. the current in the sense resistor also includes the c iss current at turn?on. this narrow spike often disturbs the controller and requires adequate treatment through a leb circuitry for instance. figure 5 represents the negative current sense technique. in this simplified example, the source directly connects to the controller ground. hence, if v cc is 8 v, the effective gate?source voltage is very close to 8 v: no sense resistor drop. how does the controller detect a negative excursion? in lack of primary current, the voltage on the cs pin reaches r offset x i cs . let us assume that these elements lead to have 1 v on this pin. now, when the power mosfet activates, the current flows via the sense resistor and develop a negative voltage by respect to the controller ground. the voltage seen on the cs is nothing else than a positive voltage (r offset x i cs ) plus the voltage across the sense resistor which is negative. thus, the cs pin vo ltage goes low as the primary current increases. when the result reaches the threshold voltage (around 20 mv), the comparator toggles and resets the main latch. figure 3 details how the voltage moves on the cs pin on a 1351 demoboard, whereas figure 7 zooms on the sense resistor voltage captured by respect to the controller ground. the choice of these two elements is simple. suppose you want to develop 1 v across the sense resistor. you would select the offset resistor via the following formula: r offset 1 i cs 1 270 3.7 k (eq. 1) if you need a peak current of 2 a, then, simply apply the ohm law to obtain the sense resistor value: r sense 1 i peak_max 1 2 0.5 (eq. 2) due to the circuit flexibility, suppose you only have access to a 0.33 resistor. in that case, the peak current will exceed the 2 a limit. why not changing the offset resistor value then? to obtain 2 a from the 0.33 resistor, you should develop: the offset resistor is thus derived by: v sense r sense i peak_max 0.33 2 660 mv (eq. 3 ) r offset 0.66 i cs 0.66 270 2.44 k (eq. 4) if reducing the sense resistor is of good practice to improve the ef ficiency, we recommend to adopt sense values between 0.5 v and 1 v. reducing the voltage below these levels will degrade the noise immunity. figure 4. positive current?sense technique c bulk + + ? i lp i lp i lp reset peak setpoint v gs i lp v sense l p drv cs r sense gnd figure 5. a simplified circuit of the negative sense implementation c bulk + + ? i lp i lp reset v sense v th i lp v dd l p drv cs r offset gnd v offset + ics
ncp1351 http://onsemi.com 9 figure 6. the voltage on the current sense pin figure 7. the voltage across the sense resistor current sense pin current sense resistor below are a few recommendations concerning the wiring and the pcb layout: ? a small 22 pf capacitor can be placed between the cs pin and the controller ground. place it as close as possible to the controller. ? do not place the offset resistor in the vicinity of the sense element, but put it close to the controller as well. ? regulation by frequency ? the power a flyback converter can deliver relates to the energy stored in the primary inductance l p and obeys the following formulae: p out_dcm 1 2 l p i peak 2 f sw (eq. 5) p out_ccm 1 2 l p ( i peak 2 i valley 2 ) f sw (eq. 6) where: (eta) is the converter efficiency i peak is the peak inductor current reached at the on time termination i valley represents the current at the end of the off time. it equals zero in dcm. f sw is the operating frequency. thus, to control the deli vered power, we can either play on the peak current setpoint (classical peak current mode control) or adjust the switching frequency by keeping the peak current constant. we have chosen the second scheme in this ncp1351 for simplicity and ease of implementation. thus, once the peak current has been selected, the feedback loop automatically reacts to satisfy equations 5 and 6. the external capacitor that you connect between pin 2 and ground (again, place it close to the controller pins) sets the maximum frequency you authorize the converter to operate up to. normalized values for this timing capacitor are 270 pf (65 khz) and 180 pf (100 khz). of course, dif ferent combinations can be tried to design at higher or lower frequencies. please note that changing the capacitor value does not affect the operating frequency at nominal line and load conditions. again, the operating frequency is selected by the feedback loop to cope with equations 5 and 6 definitions. the feedback current controls the frequency by changing the timing capacitor end of charge voltage, as illustrated by figure 8. figure 8. the current injected into the feedback loop adjusts the switching frequency i ct = 10 a controlled by the fb current v ct maximum frequency minimum frequency p out decreases p out increases
ncp1351 http://onsemi.com 10 figure 9. in light load conditions, the oscillator further delays the restart time figure 10. c t voltage swing at a moderate loading c t voltage c t voltage in light load conditions, the frequency can go down to a few hundred hz without any problem. the internal circuitry naturally blocks the oscillator and softly shifts the restart time as shown on figure 9 scope shot. delays the restart time in lack of feedback current, for instance during a startup sequence or a short circuit, the oscillator frequency is pushed to the limit set by the timing capacitor. in this case, the lower threshold imposed to the timing capacitor is blocked to 500 mv (parameter v fault ). this is the maximum power the converter can de liver. to the opposite, as you inject current via the optocoupler in the feedback pin, the off time expands and the power delivery reduces. the maximum threshold level in standby conditions is set to 6 v. over power protection as any universal?mains operated converters, the output power slightly increases at high line compared to what the power supply can deliver at low line. this discrepancy relates to the propagation delay from the point where the peak is detected to the mosfet gate effective pulldown. it naturally includes the controller reaction time, but also the driver capability to pull the gate down. if the mosfet q g is too large, then this parameter will greatly affect your overpower parameter. sometimes, the small pnp can help and we recommend it if you use a large q g mosfet: figure 11. a low?cost pnp improves the drive capability at turn?off d1 1n4148 q1 2n2907 drv gnd over power protection can be done without power dissipation penalty by arranging components around the auxiliary as suggested by figure 11. on this schematic, the diode anode swings negative during the on time. this negative level directly depends on the input voltage and offsets the current sense pin via the r opp resistor. a small integration is necessary to reduce the o pp action in light load conditions. however, depending on the compensation level, the standby power can be affected. again, the resistor r opp should be placed as close as possible to the cs pin. the 22 pf can help to circumvent any picked?up noise and d 2 prevents the positive loading of the 270 pf capacitor during the flyback swing. we have put a typical 100 k o pp resistor but a tweak is required depending on your application.
ncp1351 http://onsemi.com 11 figure 12. the opp is relatively easy to implement and it does not waste power c bulk + c3 270p r1 150k r sense drv i lp v cc l p drv cs r offset d2 1n4148 c4 22p + r opp 100k cv cc l aux d aux suppose you would need to reduce the peak current by 15% in high?line conditions. the turn?ratio between the auxiliary winding and the primary winding is n aux . assume its value is 0.15. thus, the voltage on d aux cathode swings negative during the on time to a level of: v aux_peak ?v in_max n aux ?375 0.15 ?56 v (eq. 7) if we selected a 3.7 k resistor for r offset , then the maximum sense voltage being developed is: v sense 3.7 k 270 1v (eq. 8) the small rc network made of r 1 and c 3 , purposely limits the voltage excursion on d 2 anode. assume the primary inductance value gives an on time of 3 s at high?line. the voltage across c 3 thus swings down to: v c 3 t on v aux_peak r 1 c 3 ? 3 56 150 k 270 p ?4.2 v (eq. 9) typically, we measured around ?4 v on our 50 w pro totype. by calculation, we want to decrease the peak current by 15%. compared to the internal 270 a source, we need to derive: i offset ?0.15 270 ?40.5 a (eq. 10) thus, from the ?4 v excursion, the r opp resistor is derived by: r opp 4 40.5 98 k (eq. 11) after experimental measurements, the resistor was normalized down to 100 k . feedback unlike other controllers, the feedback in the ncp1351 works in current rather than voltage. figure 13 details the internal circuitry of this particular section. the optocoupler injects a current into the fb pin in relationship with the input/output conditions.
ncp1351 http://onsemi.com 12 figure 13. the feedback section inside the ncp1351 c1 100n + ? reset v cc r fb 45k v cc d fb v offset 500mv + i fb i fb i fb fb ic t 10 c t r1 2.5k c t 270p clock i diff cs r offset 3.9k i diff = ics max ? ics min f (ifb) i diff ics min v cc c3 22pf to r sense the fb pin can actually be seen as a diode, forward biased by the optocoupler current. the feedback current, i fb on figure 13, enter an internal 45 k resistor which develops a voltage. this voltage becomes the variable threshold point for the capacitor charge, as indicated by figure 8. thus, in lack of feedback current (start?up or short?circuit), there is no voltage across the 45 k and the series offset of 500 mv clamps the capacitor swing. if a 270 pf capacitor is used, the maximum switching frequency is 65 khz. folding the frequency back at a rather high peak current can obviously generate audible noise. for this reason, the ncp1351 uses a patented current compression technique which reduces the peak current in lighter load conditions. by design, the p eak current changes from 100% of its full load value, to 30% of this value in light load conditions. this is the block placed on the lower left corner of figure 13. in full load conditions, the feedback current is weak and all the current flowing through the external offset resistor is: i cs i cs_min i dif i cs_max i cs_min (eq. 12) i cs_max as the load goes lighter, the feedback current increases and starts to steal current away from the generators. equation 12 can thus be updated by: i cs i cs_max ki fb (eq. 13) equation 13 testifies for the current reduction on the offset generator, k represents an internal coefficient. when the feedback current equals i dif , the offset becomes: i cs i cs_min (eq. 14)
ncp1351 http://onsemi.com 13 at this point, the current is fully compressed and remains frozen. to further decrease the transmitted power, the frequency does not have other choice than going down. figure 14. the ncp1351 peak current compression scheme 60 a 80 a 250 a 70 a 40 a fault (a, b versions) fb current cs current looking to the data?sheet specifications, the maximum peak current is set to 270 a whereas the compressed current goes down to 70 a. the ncp1351 can thus be considered as a multi operating mode circuit: ? real fixed peak current / variable frequency mode for fb current below 60 a. ? then maximum peak current decreases to i cs,min over a narrow linear range of i fb (to avoid instability created by a discrete jump from i cs,max to i cs,min ), between 60 a and 80 a. ? then if i fb keeps on increasing, in a real fixed peak current/variable frequency mode with reduced peak current for biasing purposes and noise immunity improvements, we recommend to wire a pulldown resistor and a capacitor in parallel from the fb pin to the controller ground (figure 15). please keep these elements as close as possible to the circuit. the pulldown resistor increases the optocoupler current but also plays a role in standby. we found that a 2.5 k resistor was giving a good tradeoff between optocoupler operating current (internal pole position) and standby power. figure 15. the recommended feedback arrangement around the fb pin c1 100nf v cc fb r1 2.5k fault detection the fault detection circuitry permanently observes the fb current, as shown on figure 17. when the feedback current decreases below 40 a, an external capacitor is charged by a 11.7 a source. as the voltage rises, a comparator detects when it reaches 5 v typical. upon detection, there can be two different scenarios: 1. a version: the circuit immediately latches?off and remains latched until the voltage on the current into the v cc pin drops below a few a. the latch is made via an internal scr circuit who holds vcc to around 6 v when fired. as long as the current flowing through this latch is above a few a, the circuit remains locked?out. when the user unplugs the converter, the v cc current falls down and resets the latch. 2. b version: the circuit stops its output pulses and the auxiliary v cc decreases via the controller own consumption ( 600 a). when it touches the v cc(min) point, the circuit re?starts and attempts to crank the power supply. if it fails again, an hiccup mode takes place (figure 13). figure 16. hiccup occurs with the b version only, the a version being latched v cc v drv the duty?burst in fault is around 7% in this particular case.
ncp1351 http://onsemi.com 14 figure 17. the internal fault management differs depending on the considered version ? + ? + c1 100n v cc i fb c timer 100nf v cc r1 2.5k + + + v timer 5 i timer 10 20 s filter p on reset d fb i fb i fb timer l aux cv cc i cc v cc d aux i fb < 40 a ? = low else = high drv pulses v cc == vcc (min) ? reset q q s to drv stage auto?recovery ? b version ? + ? + c1 100n v cc i fb c timer 100nf v cc r1 2.5k + + + v timer 5 i timer 10 20 s filter p on reset d fb i fb i fb timer l aux cv cc i cc v cc d aux i fb < 40 a ? = low else = high scr delatches when i scr < icc latch (few a) latched ? a version 6v fb fb r knowing both the ending voltage and the charge current, we can easily calculate the timer capacitor value for a given delay. suppose we need 40 ms. in that case, the capacitor is simply: c timer i timer t v timer 11.7 40 m 5 94 nf (eq. 15) select a 100 nf value. latch input the ncp1351 features a patented circuitry which prevents the fb input to be of low impedance before the vcc reaches the vcc on level. as such, the circuit can work in a primary regulation scheme. capitalizing on this typical option, figure 18 shows how to insert a zener diode in series with the optocoupler emitter pin. in that way, the current biases the zener diode and offers a nice reference voltage, appearing at the loop closure (e.g. when the output reaches the target). yes, you can use this reference voltage to supply a ntc and form a cheap otp protection. figure 18. the latch input offers everything needed to implement an otp circuit. another zener can help combining an ovp circuit if necessary c2 100n v cc r1 2.5k c1 100nf latch fb c3 100nf 5v ovp d2 r pulldown
ncp1351 http://onsemi.com 15 figure 19. you can either directly observe the v cc level or add a small rc filter to reduce the leakage inductance contribution. the best is to directly sense the output voltage and reacts if it runs away, as offered on the right side. c4 100n r4 2.2k c5 1n v cc latch c3 100nf l aux r ovp d2 1n4937 r pulldown cv cc 20 f v cc latch c3 100nf c1 100nf aux sec u1a d4 out cv cc 22 f u1b + + design example, a 19 v / 3 a universal mains power supply designing a switch?mode power supply using the ncp1351 does not differ from a fixed frequency design. what changes, however, is the regulation method via frequency variations. in other words, all the calculations must be carried at the lowest line input where the frequency will hit the maximum value set by the c t capacitor. let us follow the steps: v in min = 100 vdc (bulk valley in low?line conditions) v in max = 375 vdc v out = 19 v i out = 3 a operating mode is ccm = 0.8 f sw = 65 khz 1. turn ratio. this is the first parameter to consider. the mosfet bv dss actually dictates the amount of reflected voltage you need. if we consider a 600 v mosfet and a 15% derating factor, we must limit the maximum drain voltage to: v ds_max 600 0.85 510 v (eq. 16) knowing a maximum bulk voltage of 375 v, the clamp voltage must be set to: v clamp 510 375 135 v (eq. 17) based on the above level, we decide to adopt a headroom between the reflected voltage and the clamp level of 50 v. if this headroom is too small, a high dissipation will occur on the rdc clamp network and efficiency will suffer. a leakage inductance of around 1% of the magnetizing value should give good results with this choice (k c = 1.6). the turn ratio between primary and secondary is simply: v out v f n v clamp k c (eq. 18) solving for n gives: n n s n p k c v out v f v clamp 1.6 ( 19 0.8 ) 135 (eq. 19) 0.234 let us round it to 0.25 or 1/n = 4 figure 20. primary inductance current evolution in ccm dt sw i l t sw i peak i valley i valley i avg i 1 t 2. calculate the maximum operating duty?cycle for this flyback converter operated in ccm: d max v out n v out n v in_min 19 4 19 4 100 0.43 (eq. 20)
ncp1351 http://onsemi.com 16 in this equation, the ccm duty?cycle does not exceed 50%. the design should thus be free of subharmonic oscillations in steady?state conditions. if necessary, negative ramp compensation is however feasible by the auxiliary winding. 3. to obtain the primary inductance, we can use the following equation which expresses the inductance in relationship to a coefficient k. this coefficient actually dictates the depth of the ccm operation. if it goes to 2, then we are in dcm. l ( v in_min d max ) 2 f sw kp in (eq. 21) where k = i l /i i and defines the amount of ripple we want in ccm (see figure 20). ? small k: deep ccm, implying a large primary inductance, a low bandwidth and a large leakage inductance. ? large k: approaching bcm where the rms losses are the worse, but smaller inductance, leading to a better leakage inductance. from equation 16, a k factor of 0.8 (40% ripple) ensures a good operation over universal mains. it leads to an inductance of: l ( 100 43 ) 2 65 k 0.8 72 493 h (eq. 22) 1.34 a peak?to?peak (eq. 23) i l v in_min d max lf sw 19 3 0.8 100 the peak current can be evaluated to be: i in_avg p out v in_min 100 0.43 493 65 k 712 ma (eq. 24) i peak i avg d i l 2 0.712 0.43 1.34 2 2.33 a (eq. 25) on figure 20, i 1 can also be calculated: i i i peak i l 2 2.33 1.34 2 1.65 a (eq. 26) the valley current is also found to be: i valley i peak i l 2.33 u1.34 1.0 a (eq. 27) 4. based on the above numbers, we can now evaluate the rms current circulating in the mosfet and the sense resistor: i d_rms i i d
1 1 3 i l 2i 1 2
(eq. 28) 1.65 0.65 1 1 3 1.34 2 1.65 2
1.1 a 5. the current peaks to 2.33 a. selecting a 1 v drop across the sense resistor, we can compute its value: r sense 1 i peak 1 2.5 0.4 (eq. 29) to generate 1 v, the offset resistor will be 3.7 k , as already explained. using equation 28, the power dissipated in the sense element reaches: p sense r sense i d_rms 2 0.4 1.1 2 484 mw (eq. 30) 6. to switch at 65 khz, the c t capacitor connected to pin 2 will be selected to 180 pf. 7. as the load changes, the operating frequency will automatically adjust to satisfy either equation 5 (high power, ccm) or equation 6 in lighter load conditions (dcm). figure 21 portrays a possible application schematic implementing what we discussed in the above lines.
ncp1351 http://onsemi.com 17 figure 21. the 19 v adapter featuring the elements calculated above t1 r15 3.7k c8 270pf u1a u1b + c15 22p + c2 10n 400v r13 47k c10 0.1 r1 2.2k c9 100n r5 2.5k c4 100n + + + u2 ovp option d6 1n4148 r16 10 r6 0.4 c3 4.7 25v c1 100nf r7 1m r3 47k d3 1n4937 d2 mur 160 r4 22 r2 1m + c12 100 f 400v hv?bulk ncp1351b 1 2 3 4 8 7 6 5 25v r18 47k c17 100 6a/600v m1 l p = 500 h n p :n s = 1:0.25 n p :n aux = 0.18 d5 mbr20200 l2 2.2 v out 19v/3a c5b 1.2mf 25v c5a 1.2mf 25v c13 2.2nf type = y1 c7 220 f 25v gnd r14 2.2k r8 1k r12 4k r10 62k r9 10k gnd c6 100n ic2 tl431 on this circuit, the v cc capacitor is split in two parts, a low value capacitor (4.7 f) and a bigger one (100 f). the 4.7 f capacitor ensures a low startup time, whereas the second capacitor keeps the v cc alive in standby mode (where the switching frequency can be low). due to d 6 , it does not hamper startup time. application results we assembled a board with component values close to what is described on figure 21. here are the obtained results: p in @ no?load = 152 mw, v in = 230 vac p in @ no?load = 164 mw, v in = 100 vac the efficiency stays flat to above 80%, and keeps good even at low output levels. it clearly shows the benefit of the variable frequency implemented in the ncp1351. figure 22. efficiency measured at various operating points 72 74 76 78 80 82 84 86 88 0 0.5 1 1.5 2 2.5 3 3.5 efficiency (%) i out (a) v in = 230 vac v in = 100 vac another benefit of the variable frequency lies in the low ripple operation at no?load. this is what confirms figure 23. finally, the power supply was tested for its transient response, from 100 ma to 3 a, high and low line, with a slew?rate of 1 a/ s (figure 25). results appear in figures 25 and 26 and confirm the stability of the board.
ncp1351 http://onsemi.com 18 figure 23. no?load output ripple (v in = 230 vac) figure 24. same conditions, p out = 5 w v ds 200 v/div v out 1.0 mv/div v ds 200 v/div v out 1.0 mv/div figure 25. transient step, low line figure 26. transient step, high line v out 50 mv/div v out 50 mv/div
ncp1351 http://onsemi.com 19 package dimensions soic?8 d suffix case 751?07 issue ah seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 ncp1351/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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